The present invention relates generally to a data input/output system, and more particularly, to a memory module and a data input/output system.
Typically, a system such as a personal computer (PC), a portable multimedia device, or a mobile phone is configured to include a data input/output system in order to store data required for operation and to read stored data.
A data input/output system will typically include various types of chip sets. Examples of these chip sets include memory for data storage (for example, dynamic random access memory (DRAM)) and a memory controller for controlling the memory (for example, a central processing unit (CPU), a graphic processing unit (GPU), a memory control unit (MCU), and the like).
FIG. 1 is a block diagram illustrating a conventional data input/output system.
As shown in FIG. 1, the conventional data input/output system is configured to include a memory controller 10, a first memory module 20, a second memory module 30, a third memory module 40, and a fourth memory module 50.
Each of the first through the fourth memory modules 20, 30, 40, and 50 shown in FIG. 1 is configured as a dual in-line memory module (DIMM).
Additionally, each of the first through the fourth memory modules 20, 30, 40, and 50 is configured to include two ranks (a memory rank, for example, is a block or area of data that is created using some or all of the memory chips on a memory module). More specifically, a plurality of memory chips may be installed on one or both surfaces of each of the first through the fourth memory modules 20, 30, 40, and 50 in order to obtain a single rank or two ranks. When the plurality of memory chips is installed on both surfaces of each of the first through fourth memory modules 20, 30, 40, and 50, each of the first through the fourth memory modules 20, 30, 40, and 50 may be configured to include two ranks. When the plurality of memory chips is installed on a single surface of each of the first through fourth memory module 20, 30, 40, and 50, each of the first through the fourth memory modules 20, 30, 40, and 50 is configured to include a single rank.
The memory controller 10 commonly connects certain signal lines to the first and second memory modules 20, 30 and the third and fourth memory modules 40, 50 via channel 1 and channel 2, respectively. These signal lines are used to transmit data (DQ<0:63>), a data strobe signal DQSB, an operation command and an address (RAS, CAS, WE, ADD), and a clock signal CLK. Also, the memory controller 10 connects signal lines to the first through the fourth memory modules 20, 30, 40, and 50. The signal lines are also used to transmit chip selection signals (CS0/1, CS2/3), on die termination signals (ODT0/1, ODT2/3), and clock enable signals (CKE0/1, CKE2/3) that are classified for each rank of the first through the fourth memory modules 20, 30, 40, and 50.
When the first memory module 20 is configured to include two ranks in channel 1, two chip selection signals (CS0/1, CS2/3), two on die termination signals (ODT0/1, ODT2/3), and two clock enable signals (CKE0/1, CKE2/3) are required to selectively control the two ranks of the first memory module 20.
Additionally, four chip selection signals (CS0/1, CS2/3), on die termination signals (ODT0/1, ODT2/3), and clock enable signals (CKE0/1, CKE2/3) are required to control both the first memory module 20 and the second memory module 30 each of which includes two ranks.
Accordingly, as illustrated, the technology shown in FIG. 1 requires an additional rank selection signal (that is, a chip selection signal), an additional on die termination signal, and an additional clock enable signal for the memory extension.
The requirement of an additional signal for the memory extension leads to an increase in both the number of signal lines and the number of pins. The additional signal can also make it more difficult to control a memory module.